First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
TSV stress aware timing analysis with applications to 3D-IC layout optimization
Proceedings of the 47th Design Automation Conference
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Proceedings of the 48th Design Automation Conference
Temperature aware statistical static timing analysis
Proceedings of the International Conference on Computer-Aided Design
Through-silicon-via management during 3D physical design: when to add and how many?
Proceedings of the International Conference on Computer-Aided Design
Temperature- and Voltage-Aware Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
Proceedings of the 2014 on International symposium on physical design
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It is widely known that fabrication and thermal variations influence circuit delay. In three dimensional circuits (3D-ICs), due to the incorporation of through-silicon-vias (TSVs), thermal stress also becomes an increasing contributor to gate delay. As a result, thermal variations cause not only direct impact to the circuit parameters, they also cause 3D-IC stress variations resulting in an additional source of variability which needs to be accounted for in statistical static timing analysis (SSTA). In this paper, we study the impact (both direct and indirect - through thermal stress) of thermal variations on gate delay, and propose Monte Carlo (MC) simulation based fabrication, temperature and thermal stress variations aware SSTA methodology that accounts for this complex effect. We show that thermal stress variations cause extra -4~10% delay changes compared with the SSTA that only accounts for fabrication and direct thermal impacts, indicating that thermal stress should be considered together with direct temperature effect. We then develop a more efficient canonical thermal stress aware SSTA method that can achieve good accuracy and 843x speedup compared with MC based method.