A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Fast statistical timing analysis handling arbitrary delay correlations
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Statistical delay computation considering spatial correlations
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Considering process variations during system-level power analysis
Proceedings of the 2006 international symposium on Low power electronics and design
Prediction of leakage power under process uncertainties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An accurate sparse matrix based framework for statistical static timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature- and Voltage-Aware Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Extraction of Spatial Correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical Thermal Profile Considering Process Variations: Analysis and Applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal stress aware 3D-IC statistical static timing analysis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Incorporating the impacts of workload-dependent runtime variations into timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
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With technology scaling, the variability of device parameters continues to increase. This impacts both the performance and the temperature profile of the die turning them into a statistical distribution. To the best of our knowledge, no one has considered the impact of the statistical thermal profile during statistical analysis of the propagation delay. We present a statistical static timing analysis (SSTA) tool which considers this interdependence and produces accurate timing estimation. Our average errors for mean and standard deviation are 0.95% and 3.5% respectively when compared against Monte Carlo simulation. This is a significant improvement over SSTA that assumes a deterministic power profile, whose mean and SD errors are 3.7% and 20.9% respectively. However, when considering 90% performance yield, our algorithm's accuracy improvement was not as significant when compared to the deterministic power case. Thus, if one is concerned with the runtime, a reasonable estimate of the performance yield can be obtained by assuming nominal power. Nevertheless, a full statistical analysis is necessary to achieve maximum accuracy.