On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Electrothermal analysis of VLSI systems
Electrothermal analysis of VLSI systems
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
System level leakage reduction considering the interdependence of temperature and leakage
Proceedings of the 41st annual Design Automation Conference
Worst-case circuit delay taking into account power supply variations
Proceedings of the 41st annual Design Automation Conference
Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient full-chip thermal modeling and analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3-D Thermal-ADI: a linear-time chip level transient thermal simulator
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Closed-loop modeling of power and temperature profiles of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Temperature aware statistical static timing analysis
Proceedings of the International Conference on Computer-Aided Design
Incorporating the impacts of workload-dependent runtime variations into timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
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Circuit performance is strongly impacted by environmental conditions under which the circuit operates. In this paper, a worst-case critical path delay analysis technique is presented to consider the inter-dependencies between dynamic power, operating temperature, leakage, power supply variations and circuit delay. To allow for a realistic worst-case analysis of the critical path delays, the dynamic power consumptions of the chip-level circuit blocks are first mapped to the across-chip temperature and leakage distributions. Then, the dependency of the power supply levels along the critical path on the dynamic power consumptions is determined efficiently by locally analyzing the power grid. Finally, the worst-case critical path delay is found by solving constrained nonlinear optimization problems under the user-specified chip power consumption constrains and bounds. These constraints and bounds can be used to represent correlations between switching activities of different circuit blocks, power estimation uncertainty or various power level settings. The proposed technique is demonstrated on several benchmark circuits for which large chip-level thermal models and power grids are efficiently solved to facilitate the required worst-case analysis.