Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Sub-90nm technologies: challenges and opportunities for CAD
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 40th annual Design Automation Conference
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
EDA challenges facing future microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stochastic Power Grid Analysis Considering Process Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
VLSI on-chip power/ground network optimization considering decap leakage currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Stochastic variational analysis of large power grids considering intra-die correlations
Proceedings of the 43rd annual Design Automation Conference
Accurate power grid analysis with behavioral transistor network modeling
Proceedings of the 2007 international symposium on Physical design
Analysis of Power Supply Noise in the Presence of Process Variations
IEEE Design & Test
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient decoupling capacitance budgeting considering operation and process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Generating realistic stimuli for accurate power grid analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical analysis of large on-chip power grid networks by variational reduction scheme
Integration, the VLSI Journal
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Transistor threshold voltages (V{th}) have been reduced as partof on-going technology scaling. The smaller V{th} values featureincreased variations due to underlying process variations, witha strong within-die component. Correspondingly, given the exponential dependence of leakage on V{th}, circuit leakage currentsare increasing significantly and have strong within-die statistical variations.With these leakage currents loading the powergrid, the grid develops correspondingly large statistical voltagedrops. This leakage-induced voltage drop is an unavoidable background level of noise on the grid. Any additional non-leakagecurrents due to circuit activity will lead to voltage drop which isto be added to this background noise. We propose a techniquefor checking whether the statistical voltage drop on every node iswithin user-specified bounds, given user-specified statistics of theleakage currents.