Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A power macromodeling technique based on power sensitivity
DAC '98 Proceedings of the 35th annual Design Automation Conference
The design of a SRAM-based field-programmable gate array—part II: circuit design and layout
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electrothermal analysis of VLSI systems
Electrothermal analysis of VLSI systems
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
On-chip thermal engineering for peta-scale integration
Proceedings of the 2002 international symposium on Physical design
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Performance-driven placement for dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thermal monitoring on FPGAs using ring-oscillators
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Microarchitecture level power and thermal simulation considering temperature dependent leakage model
Proceedings of the 2003 international symposium on Low power electronics and design
LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
System level leakage reduction considering the interdependence of temperature and leakage
Proceedings of the 41st annual Design Automation Conference
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cycle-Accurate Energy Measurement and Characterization of FPGAs
Analog Integrated Circuits and Signal Processing
Efficient full-chip thermal modeling and analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Methodology for high level estimation of FPGA power consumption
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal Trends in Emerging Technologies
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs
Proceedings of the 2006 international symposium on Low power electronics and design
Thermal characterization and optimization in platform FPGAs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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In recent times, the contribution of leakage power to the total power consumption of a chip has been increasing at an alarming rate. Leakage power is expected to exceed dynamic power in newer process technologies. Since leakage exhibits an exponential increase with temperature, it is possible that the high leakage of an IC causes a temperature increase, which in turn causes an increase in leakage, and so on, until the IC fails due to overheating. At the very least, this may cause the temperature and power consumption of the IC to be poorly estimated by traditional thermal or power modeling techniques. We developed a framework to model this situation in an FPGA context. Our CAD framework accurately models the total power consumption of the design at a given temperature, finds the thermal profile of the IC under this power consumption, and then uses this new thermal information to update the power consumption. This is iterated until the temperature of the IC converges, or until the temperatures on the die exceed a safe value. The iterations are very fast, due to the use of accurate and compact mathematical macromodels for leakage and temperature computation in the inner loop. We have exhaustively verified the fidelity of all our leakage macromodels. They estimate the leakage, at any temperature, to within 3% of the values generated by SPICE, while providing greater than four orders of magnitude speedup over explicit SPICE runs. Our experiments show that this model helps avoid an incorrect estimation of chip temperature and total power consumption, and also helps detect the increase in device temperature beyond a safe value. The average (maximum) error of our temperature estimates has been found to be within 1% (2.5%) compared to a full-chip 3D temperature modeling tool.