A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
An empirical model for accurate estimation of routing delay in FPGAs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Practical low power digital VLSI design
Practical low power digital VLSI design
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Pre-layout estimation of individual wire lengths
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Power and delay reduction via simultaneous logic and placement optimization in FPGAs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Low-energy FPGAs: architecture and design
Low-energy FPGAs: architecture and design
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Estimating Circuit Activity in Combinational CMOS Digital Circuits
IEEE Design & Test
Switching activity analysis and pre-layout activity prediction for FPGAs
Proceedings of the 2003 international workshop on System-level interconnect prediction
Proceedings of the 2003 international symposium on Physical design
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FPGA Technology Mapping for Power Minimization
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Fast timing-driven partitioning-based placement for island style FPGAs
Proceedings of the 40th annual Design Automation Conference
Adaptive delay estimation for partitioning-driven PLD placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Interconnect capacitance estimation for FPGAs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Closed-loop modeling of power and temperature profiles of FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2009 International Conference on Computer-Aided Design
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-aware, depth-optimum and area minimization mapping of K-LUT based FPGA circuits
WSEAS Transactions on Computers
Empirical method based on neural networks for analog power modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Simulation Framework for Rapid Analysis of Reconfigurable Computing Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power estimation of embedded multiplier blocks in FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analytical model relating FPGA architecture parameters to routability
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Total power modeling in FPGAs under spatial correlation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power estimation of dividers implemented in FPGAs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A complete dynamic power estimation model for data-paths in FPGA DSP designs
Integration, the VLSI Journal
Power dissipation impact of the technology mapping synthesis on look-up table architectures
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). We then describe a novel approach for prelayout activity prediction that estimates a net's routed delay activity using only zero or logic delay activity values, along with structural and functional circuit properties. For capacitance prediction, we show that prediction accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also demonstrate that there is an inherent variability (noise) in the switching activity and capacitance of nets that limits the accuracy attainable in prediction. Experimental results show the proposed prediction models work well given the noise limitations.