Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power FPGA design—a re-engineering approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
FPGA Technology Mapping for Power Minimization
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Scheduling with integer time budgeting for low-power optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Real time generation of the Quinquenary pulse compression sequence using FPGA
WSEAS Transactions on Signal Processing
WSEAS Transactions on Circuits and Systems
On K-LUT based FPGA optimum delay and optimal area mapping
MACMESE'08 Proceedings of the 10th WSEAS international conference on Mathematical and computational methods in science and engineering
Sa based power efficient FPGA LUT mapping
Proceedings of the 15th annual conference companion on Genetic and evolutionary computation
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This paper introduces an efficient application intended for mapping under complex criteria applied to K-LUT based FPGA implemented circuits. This application is based on an algorithm that was developed taking into consideration a significant design factor - power consumption. Power consumption is considered in addition to other design factors that are traditionally used. To increase performance, it was used a flexible mapping tool based on exhaustive generation of all K-bounded sub-circuits rooted in each node of the circuit. Achieved information about logic dissipated power was obtained using an efficient dedicated simulator. In addition to lower power consumption, we devised several effective mapping techniques designed for reducing area and optimum depth.