Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads

  • Authors:
  • Phillip H. Jones;Young H. Cho;John W. Lockwood

  • Affiliations:
  • Washington University, St. Louis, MO;Washington University, St. Louis, MO;Washington University, St. Louis, MO

  • Venue:
  • VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
  • Year:
  • 2007

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Abstract

In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed excessive power. Today, the temperature of FPGAs are a major concern due to increased logic density and speed. Large applications with highly pipelined datapaths can ultimately generate more heat than the package can dissipate. For FPGAs that operate in controlled environments, heat sinks and fans can be used to effectively dissipate heat from the device. However, FPGA devices operating under harsher thermal conditions in outdoor environments, or in systems with malfunctioning cooling systems need a thermal management control system. To address this issue, we had previously devised a recon- figurable temperature monitoring system that gives feedback to the FPGA circuit using the measured junction temperature of the device. Using this feedback, we designed a novel dual frequency switching system that allows the FPGA circuits to maintain the highest level of throughput performance for a given maximum junction temperature. This paper extends the previous work by additionally making this adaptive frequency mechanism workload aware and evaluating power and latency performance under bursty workload conditions. Our working system has been implemented on the Field Programmable Port Extender (FPX) platform developed at Washington University in St. Louis. Experimental results with a scalable image correlation circuit show up to a 30% saving in power for bursty workloads and up to a 2x factor improvement in latency performance as compared to a system without thermal or workload feedback. Our circuit provides power efficient high performance processing of bursty workloads, while ensuring the device always operates within a safe temperature range.