Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algorithms for the Simple Equal Flow Problem
Management Science
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Analysis and reduction of glitches in synchronous networks
EDTC '95 Proceedings of the 1995 European conference on Design and Test
High-Level Power Modeling of CPLDs and FPGAs
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
High-level synthesis for low power based on network flow method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Interconnect-based system-level energy and power prediction to guide architecture exploration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
Scheduling with integer time budgeting for low-power optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Power-aware, depth-optimum and area minimization mapping of K-LUT based FPGA circuits
WSEAS Transactions on Computers
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In this paper we discuss optimizing the interconnect power of designs implemented in FPGA platforms. In particular, we reduce the glitch power on interconnects associated with the output of functional units in a design. The idea is to activate unused flip-flops to block the propagation of glitches, which takes advantage of the abundant flip-flops in modern FPGA structures. Since the activation of additional flip-flops may cause data hazard problems, we develop several effective behavioral synthesis techniques to prevent such data hazards. We also study the optimality of our techniques. The experimental results show that on average, our methods lead to a 28% reduction in dynamic power in the Xilinx Virtex-II platform.