Architectural strategies for high-throughput applications
Journal of VLSI Signal Processing Systems - Special issue: video/image signal processing
Efficient timing constraint derivation for optimal retiming high speed processing units
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
New approach in gate-level glitch modelling
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Short circuit power consumption of glitches
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power-simulation of cell based ASICs: accuracy-and performance trade-offs
Proceedings of the conference on Design, automation and test in Europe
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits
IEEE Transactions on Computers
Impact of Voltage Scaling on Glitch Power Consumption
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Using negative edge triggered ffs to reduce glitching power in FPGA circuits
Proceedings of the 44th annual Design Automation Conference
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Tracking the pipelining-power rule along the FPGA technical literature
Proceedings of the 10th FPGAworld Conference
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The influence of transition activity on dynamic power dissipation is analysed by examining three components: dissipation in combinational logic, flipflops and clock line. Transition activity is analysed by making a distinction between useful transitions and glitches (useless transitions). A transition counting and parity evaluation method is used for this. Most glitches can be eliminated by introducing flipflops using retiming and pipelining and/or by choosing different architectures. In this way an optimal level for pipelining can be found.