Impact of Voltage Scaling on Glitch Power Consumption

Authors:
Henrik Eriksson;Per Larsson-Edefors
Affiliations:
-;-
Venue:
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Year:
2000

Citing 3
Cited 0

Digital integrated circuits: a design perspective

Digital integrated circuits: a design perspective
Analysis and reduction of glitches in synchronous networks

EDTC '95 Proceedings of the 1995 European conference on Design and Test
Register transfer level power optimization with emphasis on glitch analysis and reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

To be able to predict the importance of glitches in future deep-submicron processes with lowered supply and threshold voltages, a study has been conducted on designs, which experience glitching, at supply voltages in the range from 3.5 V to 1.0 V. The results show that the dynamic power consumption caused by glitches will, in comparison to the dynamic power consumption of transitions, be at least as important in the future as it is today.