On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Some Notes on Power Management on FPGA-Based Systems
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Analysis and reduction of glitches in synchronous networks
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Circuit implementation of high-speed pipeline systems
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
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This work reviews the contributions of power-oriented pipelining over the last two decades, and adds up-to-date results on 65 nm and 45 nm FPGAs. The data show that power consumption can be reduced by a factor between 0.1 and 0.8 using different levels of pipelining. More than 34 experiments, developed in 12 laboratories in 8 countries during 17 years are summarized. This paper also contributes to this research topic adding updated results for Altera 65 nm Cyclone III and Xilinx 45 nm Spartan-6 devices.