Mathematical statistics (4th ed.)
Mathematical statistics (4th ed.)
Planning a computer system: Project Stretch
Planning a computer system: Project Stretch
Design considerations for a 25-nanosecond tunnel diode memory
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
The model 92 as a member of the system/360 family
AFIPS '64 (Fall, part II) Proceedings of the October 27-29, 1964, fall joint computer conference, part II: very high speed computer systems
A 10 Mc NDRO BIAX memory of 1024 word, 48 bit per word capacity
AFIPS '64 (Fall, part I) Proceedings of the October 27-29, 1964, fall joint computer conference, part I
Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Synthesis of optimal clocking schemes
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Single-transistor transparent-latch clocking
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A Scheme for Synchronizing High-Speed Logic Part II
IEEE Transactions on Computers
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
Pipelining of Arithmetic Functions
IEEE Transactions on Computers
Tracking the pipelining-power rule along the FPGA technical literature
Proceedings of the 10th FPGAworld Conference
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The implementation of high-speed pipeline systems as described in this paper arose as a direct consequence of a large scale Department of Defense developmental effort initiated in 1962. The objective of the effort was to develop and make available a complete capability for producing individual special-purpose systems on a fast reaction basis. From 1962 to the present time attention was focused on all aspects of circuit and packaging technology, automated or computerized design aids, feasibility vehicling, systems design studies, and advanced memory development. As a result of strong industry impetus in these directions it now appears that 1 to 2 nanosecond hybrid integrated or full integrated logic circuits, practical fabrication of transmission line interconnections, packaging densities of 5000 logic gates per cubic foot in the machine environment, 100 to 150 nanosecond cycle time DRO thin film main memories, and 23 to 40 nanosecond integrated scratchpad memories will be made available for systems being constructed over the next one to three year period.