On average power dissipation and random pattern testability of CMOS combinational logic networks

Low power design and its testability

ATS '95 Proceedings of the 4th Asian Test Symposium

Optimization of combinational and sequential logic circuits for low power using precomputation

ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)

Decomposition of logic functions for minimum transition activity

EDTC '95 Proceedings of the 1995 European conference on Design and Test

20.3 A Test Pattern Generation Methodology for Low-Power Consumption

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

A Test Vector Inhibiting Technique for Low Energy BIST Design

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Using negative edge triggered ffs to reduce glitching power in FPGA circuits

Proceedings of the 44th annual Design Automation Conference

Superpipelined high-performance optical-flow computation architecture

Computer Vision and Image Understanding

Dynamic power estimation for deep submicron circuits with process variation

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Tracking the pipelining-power rule along the FPGA technical literature

Proceedings of the 10th FPGAworld Conference