Superpipelined high-performance optical-flow computation architecture

  • Authors:

  • Javier Díaz;Eduardo Ros;Rodrigo Agís;Jose Luis Bernier

  • Affiliations:

  • Department of Computer Architecture and Technology, University of Granada, E.T.S.I. Informática, C/Periodista Daniel Saucedo, s/n., E-18071 Granada, Spain;Department of Computer Architecture and Technology, University of Granada, E.T.S.I. Informática, C/Periodista Daniel Saucedo, s/n., E-18071 Granada, Spain;Department of Computer Architecture and Technology, University of Granada, E.T.S.I. Informática, C/Periodista Daniel Saucedo, s/n., E-18071 Granada, Spain;Department of Computer Architecture and Technology, University of Granada, E.T.S.I. Informática, C/Periodista Daniel Saucedo, s/n., E-18071 Granada, Spain

  • Venue:
  • Computer Vision and Image Understanding
  • Year:
  • 2008

Quantified Score

Hi-index 0.00

Visualization

Abstract

Optical-flow computation is a well-known technique and there are important fields in which the application of this visual modality commands high interest. Nevertheless, most real-world applications require real-time processing, an issue which has only recently been addressed. Most real-time systems described to date use basic models which limit their applicability to generic tasks, especially when fast motion is presented or when subpixel motion resolution is required. Therefore, instead of implementing a complex optical-flow approach, we describe here a very high-frame-rate optical-flow processing system. Recent advances in image sensor technology make it possible nowadays to use high-frame-rate sensors to properly sample fast motion (i.e. as a low-motion scene), which makes a gradient-based approach one of the best options in terms of accuracy and consumption of resources for any real-time implementation. Taking advantage of the regular data flow of this kind of algorithm, our approach implements a novel superpipelined, fully parallelized architecture for optical-flow processing. The system is fully working and is organized into more than 70 pipeline stages, which achieve a data throughput of one pixel per clock cycle. This computing scheme is well suited to FPGA technology and VLSI implementation. The developed customized DSP architecture is capable of processing up to 170 frames per second at a resolution of 800x600 pixels. We discuss the advantages of high-frame-rate processing and justify the optical-flow model chosen for the implementation. We analyze this architecture, measure the system resource requirements using FPGA devices and finally evaluate the system's performance and compare it with other approaches described in the literature.