Synthesis of saturation arithmetic architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimum and heuristic synthesis of multiple word-length architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
IEEE Transactions on Computers
Précis: A Usercentric Word-Length Optimization Tool
IEEE Design & Test
Word-length optimization for differentiable nonlinear systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Superpipelined high-performance optical-flow computation architecture
Computer Vision and Image Understanding
Integrated floorplanning, module-selection, and architecture generation for reconfigurable devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accuracy constraint determination in fixed-point system design
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
SQNR estimation of fixed-point DSP algorithms
EURASIP Journal on Advances in Signal Processing
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This paper introduces a design tool and its associatedprocedures for determining the sensitivity of outputs in adigital signal processing design to small errors introducedby rounding or truncation of internal variables. The proposedapproach can be applied to both linear and nonlineardesigns. By analyzing the resulting sensitivity values,the proposed procedure is able to determine an appropriatedistinct word-length for each internal variable. Alsoin this paper, the power-optimizing capabilities of word-lengthoptimization are studied for the first time. Applicationof the proposed procedure to adaptive filters realizedin a Xilinx Virtex FPGA has resulted in area reductions ofup to 80% combined with power reductions of up to 98%and speed-up of up to 36% over common alternative designstrategies.