System level fixed-point design based on an interpolative approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Low-power behavioral synthesis optimization using multiple precision arithmetic
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Bidwidth analysis with application to silicon compilation
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Digital Signal Processing: A Computer Based Approach
Digital Signal Processing: A Computer Based Approach
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Perturbation Analysis for Word-length Optimization
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
The Multiple Wordlength Paradigm
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A compact DSP core with static floating-point unit & its microcode generation
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Compact DSP Core with Static Floating-Point Arithmetic
Journal of VLSI Signal Processing Systems
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
ICIC'09 Proceedings of the 5th international conference on Emerging intelligent computing technology and applications
Domain-Specific Optimization of Signal Recognition Targeting FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Encoding OCL data types for SAT-based verification of UML/OCL models
TAP'11 Proceedings of the 5th international conference on Tests and proofs
Using type analysis in compiler to mitigate integer-overflow-to-buffer-overflow threat
Journal of Computer Security - ESORICS 2010
| Hi-index | 0.00 |
This paper describes a synthesis technique for automating the design of linear Digital Signal Processing (DSP) systems such as digital filters. The proposed methodology makes optimized use of saturation arithmetic to produce a small design implemented directly in hardware. An analytical technique is proposed to estimate the saturation error resulting from a particular implementation, and an optimization procedure is introduced to aim for the smallest implementation satisfying user-specified bounds on saturation and roundoff error. Results are presented illustrating significant speedup and area reduction compared with standard DSP design techniques: up to 22% improvement in area and 28% improvement in speed have been obtained on Field Programmable Gate Array (FPGA) implementations.