Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
JPEG Still Image Data Compression Standard
JPEG Still Image Data Compression Standard
Proceedings of the 40th annual Design Automation Conference
Synthesis of saturation arithmetic architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DSP-based architectures for mobile communications: past, present and future
IEEE Communications Magazine
Multiprocessor frequency locking for real-time task synchronization
Proceedings of the 2008 ACM symposium on Applied computing
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
International Journal of Computational Science and Engineering
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A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must have some overlapped (and redundant) components with the host microprocessor. This paper presents a compact DSP for multi-core systems, which is fully programmable and has been optimized to execute a set of signal processing kernels very efficiently. The DSP core was designed concurrently with its automatic software generator based on high-level synthesis. Moreover, it performs lightweight arithmetic--the static floating-point (SFP), which approximates the quality of floating-point (FP) operations with the hardware similar to that of the integer arithmetic. In our simulations, the compact DSP and its auto-generated software can achieve 3X performance (estimated in cycles) of those DSP cores in the dual-core baseband processors with similar computing resources. Besides, the 16-bit SFP has above 40 dB signal to round-off noise ratio over the IEEE single-precision FP, and it even outperforms the hand-optimized programs based on the 32-bit integer arithmetic. The 24-bit SFP has above 64 dB quality, of which the maximum precision is identical to that of the single-precision FP. Finally, the DSP core has been implemented and fabricated in the UMC 0.18µm 1P6M CMOS technology. It can operate at 314.5 MHz while consuming 52mW average power. The core size is only 1.5 mm脳1.5 mm including the 16 KB on-chip memory and the AMBA AHB interface.