Reducing power by optimizing the necessary precision/range of floating-point arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Fuzzy Memoization for Floating-Point Multimedia Applications
IEEE Transactions on Computers
A Compact DSP Core with Static Floating-Point Arithmetic
Journal of VLSI Signal Processing Systems
Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support
IEEE Transactions on Computers
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With the rapid growth of floating-point FP arithmetic, FP multipliers have become the main energy consumers in embedded systems. Many FP applications allow a slight output distortion, thereby we can trade output quality with energy consumption via reducing the precision of FP multiplication operations to be less accurate than IEEE single-precision FP multiplication. In this paper, we propose a sort of multi-mode FP iterative booth multiplier which can provide multiple precision modes PMs. However, the maximum error of each PM with respect to IEEE single-precision FP multiplication is very difficult to compute by using exhaustive simulation. To efficiently assign each multiplication operation in an application to a proper PM for satisfying output error constraint and achieving more energy saving, an exact analysis method is proposed to estimate the maximum error of each PM. Experimental results show that the proposed method can get 46% to 63% reduction in the estimated value of the maximum error, leading to up to 24% more energy saving than previous work.