Reducing power by optimizing the necessary precision/range of floating-point arithmetic

  • Authors:
  • Jonathan Ying Fai Tong;David Nagle;Rob. A. Rutenbar

  • Affiliations:
  • Motorola, Austin, TX;Carnegie-Mellon Univ., Pittsburgh, PA;Carnegie-Mellon Univ., Pittsburgh, PA

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
  • Year:
  • 2000

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Abstract

Low-power systems often find the power cost of floating-point (FP) hardware prohibitively expensive. This paper explores ways of reducing FP power consumption by minimizing the bitwidth representation of FP data. Analysis of several FP programs that manipulate low-resolution human sensory data shows that these programs suffer no loss of accuracy even with a significant reduction in bitwidth. Most FP programs in our benchmark suite maintain the same output even when the mantissa bitwidth is reduced by half. This FP bitwidth reduction can deliver a significant power saving through the use of a variable bitwidth FP unit. Our results show that up to 66% reduction in multiplier energy/operation can be achieved in the FP unit by this bitwidth reduction technique without sacrificing any program accuracy.