Automating Customisation of Floating-Point Designs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Determining appropriate precisions for signals in fixed-point IIR filters
Proceedings of the 40th annual Design Automation Conference
Synthesis of saturation arithmetic architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimum and heuristic synthesis of multiple word-length architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
IEEE Transactions on Computers
Précis: A Usercentric Word-Length Optimization Tool
IEEE Design & Test
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Word-length optimization beyond straight line code
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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This paper presents a paradigm for the design of multiple wordlength parallel processing systems for DSP applications based on varying the wordlength and scaling of each signal in a DSP block diagram. A technique for estimating the observable effects of truncation and roundoff error is illustrated, and used to form the basis of an optimization algorithm to automate the design of such multiple wordlength systems. Results from implementation on a reconfigurable computing platform show that significant logic usage savings and increased clock rates can be obtained by customizing the datapath precision to the algorithm according to the techniques described in this paper. On selected DSP benchmarks, we obtain up to 45% area reduction and up to 39% speed increase over standard design techniques.