The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
The art of computer programming, volume 1 (3rd ed.): fundamental algorithms
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Accuracy Sensitive Word--Length Selection for Algorithm Optimization
ICCD '98 Proceedings of the International Conference on Computer Design
High-Level Power Modeling of CPLDs and FPGAs
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Perturbation Analysis for Word-length Optimization
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Macro-models for high level area and power estimation on FPGAs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Multiple Wordlength Paradigm
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Word-length optimization for differentiable nonlinear systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Simulation-based word-length optimization method for fixed-pointdigital signal processing systems
IEEE Transactions on Signal Processing
Activity-sensitive architectural power analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accuracy-Guaranteed Bit-Width Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This article describes the first method for minimizing the dynamic power consumption of a Digital Signal Processing (DSP) algorithm implemented on reconfigurable hardware via word-length optimization. Fast models for estimating the power consumption of the arithmetic components and the routing power of these algorithm implementations are used within a constrained nonlinear optimization formulation that solves a relaxed version of word-length optimization. Tight lower and upper bounds on the cost of the integer word-length problem can be obtained using the proposed solution, with typical upper bounds being 2.9% and 5.1% larger than the lower bounds for area and power consumption, respectively. Heuristics can then use the upper bound as a starting point from which to get even closer to the known lower bound. Results show that power consumption can be improved by up to 40% compared to that achieved when using simple word-length selection techniques, and further comparisons are made between the minimization of different cost functions that give insight into the advantages offered by multiple word-length optimization.