Energy-optimized image communication on resource-constrained sensor platforms
Proceedings of the 6th international conference on Information processing in sensor networks
A flexible architecture for precise gamma correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Symbolic noise analysis approach to computational hardware optimization
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accelerating seismic computations using customized number representations on FPGAs
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient image compression for resource-constrained platforms
IEEE Transactions on Image Processing
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Fast trade-off evaluation for digital signal processing systems during wordlength optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Towards program optimization through automated analysis of numerical precision
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
Computational bit-width allocation for operations in vector calculus
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Bit-width allocation for hardware accelerators for scientific computing using SAT-modulo theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Externally linear time invariant digital signal processors
IEEE Transactions on Signal Processing
Tradeoff between Approximation Accuracy and Complexity for Range Analysis using Affine Arithmetic
Journal of Signal Processing Systems
Finite precision bit-width allocation using SAT-modulo theory
Proceedings of the Conference on Design, Automation and Test in Europe
SQNR estimation of fixed-point DSP algorithms
EURASIP Journal on Advances in Signal Processing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
Journal of Signal Processing Systems
Trustworthy numerical computation in Scala
Proceedings of the 2011 ACM international conference on Object oriented programming systems languages and applications
Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits
Proceedings of the International Conference on Computer-Aided Design
A scalable approach for automated precision analysis
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Energy reduction by systematic run-time reconfigurable hardware deactivation
Transactions on High-Performance Embedded Architectures and Compilers IV
Multi-level customisation framework for curve based monte carlo financial simulations
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Optimising performance of quadrature methods with reduced precision
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
A bit too precise? bounded verification of quantized digital filters
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Synthesis of minimal-error control software
Proceedings of the tenth ACM international conference on Embedded software
The CRNS framework and its application to programmable and reconfigurable cryptography
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Word-length optimization beyond straight line code
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Enriching MATLAB with aspect-oriented features for developing embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Synthesis of fixed-point programs
Proceedings of the Eleventh ACM International Conference on Embedded Software
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An automated static approach for optimizing bit widths of fixed-point feedforward designs with guaranteed accuracy, called MiniBit, is presented. Methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing the circuit area are described. For range analysis, the technique in this paper identifies the number of integer bits necessary to meet range requirements. For precision analysis, a semianalytical approach with analytical error models in conjunction with adaptive simulated annealing is employed to optimize the number of fraction bits. The analytical models make it possible to guarantee overflow/underflow protection and numerical accuracy for all inputs over the user-specified input intervals. Using a stream compiler for field-programmable gate arrays (FPGAs), the approach in this paper is demonstrated with polynomial approximation, RGB-to-YCbCr conversion, matrix multiplication, B-splines, and discrete cosine transform placed and routed on a Xilinx Virtex-4 FPGA. Improvements for a given design reduce the area and the latency by up to 26% and 12%, respectively, over a design using optimum uniform fraction bit widths. Studies show that MiniBit-optimized designs are within 1% of the area produced from the integer linear programming approach