A Metalgorithm for Adaptive Quadrature
Journal of the ACM (JACM)
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
MiniBit: bit-width optimization via affine arithmetic
Proceedings of the 42nd annual Design Automation Conference
Numerical integration of the three-dimensional Green kernel for an electromagnetic problem
Journal of Computational Physics
Automated Precision Analysis: A Polynomial Algebraic Approach
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Finite precision bit-width allocation using SAT-modulo theory
Proceedings of the Conference on Design, Automation and Test in Europe
Mixed Precision Processing in Reconfigurable Systems
FCCM '11 Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ASC: a stream compiler for computing with FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accuracy-Guaranteed Bit-Width Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parametric optimization of reconfigurable designs using machine learning
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
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This paper presents a generic precision optimisation methodology for quadrature computation targeting reconfigurable hardware to maximise performance at a given error tolerance level. The proposed methodology optimises performance by considering integration grid density versus mantissa size of floating-point operators. The optimisation provides the number of integration points and mantissa size with maximised throughput while meeting given error tolerance requirement. Three case studies show that the proposed reduced precision designs on a Virtex-6 SX475T FPGA are up to 6 times faster than comparable FPGA designs with double precision arithmetic. They are up to 15.1 times faster and 234.9 times more energy efficient than an i7-870 quad-core CPU, and are 1.2 times faster and 42.2 times more energy efficient than a Tesla C2070 GPU.