A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 40th annual Design Automation Conference
Automatic Evaluation of the Accuracy of Fixed-Point Algorithms
Proceedings of the conference on Design, automation and test in Europe
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis
IEEE Transactions on Computers
A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation
IEEE Transactions on Computers
Statistical noise margin estimation for sub-threshold combinational circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Bit-width allocation for hardware accelerators for scientific computing using SAT-modulo theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimising performance of quadrature methods with reduced precision
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Small gestures go a long way: how many bits per gesture do recognizers actually need?
Proceedings of the Designing Interactive Systems Conference
Word-length optimization beyond straight line code
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
The impact of motion dimensionality and bit cardinality on the design of 3D gesture recognizers
International Journal of Human-Computer Studies
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MiniBit, our automated approach for optimizing bit-widths of fixed-point designs is based on static analysis via affine arithmetic. We describe methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing circuit area. Our range analysis technique identifies the number of integer bits required. For precision analysis, we employ a semi-analytical approach with analytical error models in conjunction with adaptive simulated annealing to find the optimum number of fraction bits. Improvements for a given design reduce area and latency by up to 20% and 12% respectively, over optimum uniform fraction bit-widths on a Xilinx Virtex-4 FPGA.