Discrete-time signal processing
Discrete-time signal processing
Multirate systems and filter banks
Multirate systems and filter banks
A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Efficient Wordlength Reduction Techniques for DSP Applications
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
IEEE Computational Science & Engineering
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
MiniBit: bit-width optimization via affine arithmetic
Proceedings of the 42nd annual Design Automation Conference
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
IEEE Transactions on Computers
Symbolic noise analysis approach to computational hardware optimization
Proceedings of the 45th annual Design Automation Conference
Simulation-based word-length optimization method for fixed-pointdigital signal processing systems
IEEE Transactions on Signal Processing
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Filters datapath signals and coefficients are quantised when implemented in hardware to limit and reduce excessive hardware requirements. In this paper, we formulate quantisation errors (noises) in fixed-point arithmetic using a novel analytical model. The latter extends a conventional signal quantisation statistical model by assuming a Gaussian distribution noise. The paper gives the mathematical expressions to compute the statistical parameters and range values of the quantisation errors at any point in a multistage FIR filters structure depending on the wordlengths fractional precisions. Three case studies are included to vindicate the model@?s validity and accuracy in predicting the quantisation error parameters in the absence of filter coefficients quantisation. To counter the effects of the latter, we present a novel approach, called errors cancellation. The approach tends to represent the filter coefficients using different wordlengths to minimise the dynamic of the error filter@?s output. This allows limiting the quantisation effects to the signals quantisation only, which is statistically accurately modelled. The validity and the efficiency of the approach along with our analytical model are shown using two further case studies. Through our errors cancellation approach and analytical model, a hardware designer can now minimise the effects of the filter coefficients quantisation and predict subsequently the range values of the computation errors depending on the fractional precision used. He can also preset the latter to achieve the sought computations accuracy.