Accuracy and Stability of Numerical Algorithms
Accuracy and Stability of Numerical Algorithms
Automating Customisation of Floating-Point Designs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automated Least-Significant Bit Datapath Optimization for FPGAs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
The Multiple Wordlength Paradigm
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
MiniBit: bit-width optimization via affine arithmetic
Proceedings of the 42nd annual Design Automation Conference
Termination proofs for systems code
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Discovering non-linear ranking functions by solving semi-algebraic systems
ICTAC'07 Proceedings of the 4th international conference on Theoretical aspects of computing
Robust design methods for hardware accelerators for iterative algorithms in scientific computing
Proceedings of the 47th Design Automation Conference
SQNR estimation of fixed-point DSP algorithms
EURASIP Journal on Advances in Signal Processing
Certifying the Floating-Point Implementation of an Elementary Function Using Gappa
IEEE Transactions on Computers
Communications of the ACM
Numerical Data Representations for FPGA-Based Scientific Computing
IEEE Design & Test
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
A scalable approach for automated precision analysis
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
ARMC: the logical choice for software model checking with abstraction refinement
PADL'07 Proceedings of the 9th international conference on Practical Aspects of Declarative Languages
Ranking function synthesis for bit-vector relations
TACAS'10 Proceedings of the 16th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Termination analysis of imperative programs using bitvector arithmetic
VSTTE'12 Proceedings of the 4th international conference on Verified Software: theories, tools, experiments
Simulation-based word-length optimization method for fixed-pointdigital signal processing systems
IEEE Transactions on Signal Processing
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accuracy-Guaranteed Bit-Width Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bounding Variable Values and Round-Off Effects Using Handelman Representations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The silicon area benefits that result from word-length optimization have been widely reported by the FPGA community. However, to date, most approaches are restricted to straight line code, or code that can be converted into straight line code using techniques such as loop-unrolling. In this paper, we take the first steps towards creating analytical techniques to optimize the precision used throughout custom FPGA accelerators for algorithms that contain loops with data dependent exit conditions. To achieve this, we build on ideas emanating from the software verification community to prove program termination. Our idea is to apply word-length optimization techniques to find the minimum precision required to guarantee that a loop with data dependent exit conditions will terminate. Without techniques to analyze algorithms containing these types of loops, a hardware designer may elect to implement every arithmetic operator throughout a custom FPGA-based accelerator using IEEE-754 standard single or double precision arithmetic. With this approach, the FPGA accelerator would have comparable accuracy to a software implementation. However, we show that using our new technique to create custom fixed and floating point designs, we can obtain silicon area savings of up to 50% over IEEE standard single precision arithmetic, or 80% over IEEE standard double precision arithmetic, at the same time as providing guarantees that the created hardware designs will work in practice.