Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
HySAT: An efficient proof engine for bounded model checking of hybrid systems
Formal Methods in System Design
Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Finite precision bit-width allocation using SAT-modulo theory
Proceedings of the Conference on Design, Automation and Test in Europe
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scalable approach for automated precision analysis
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Word-length optimization beyond straight line code
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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The ubiquity of embedded systems of increasing complexity in domains like scientific computing requires computation on models whose complexity has grown beyond what is economical to manage purely in software to requiring hardware acceleration - a key part of which is selecting numerical data representations (bit-width allocation). To address the shortcomings of existing techniques when applied to scientific computing dataflows, we propose a methodology for determining custom hybrid fixed/floating-point data representations for iterative scientific computing applications.