A Simple but Realistic Model of Floating-Point Computation
ACM Transactions on Mathematical Software (TOMS)
Accuracy and Stability of Numerical Algorithms
Accuracy and Stability of Numerical Algorithms
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automated Least-Significant Bit Datapath Optimization for FPGAs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Floating-point sparse matrix-vector multiply for FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Assisted verification of elementary functions using Gappa
Proceedings of the 2006 ACM symposium on Applied computing
Elementary Functions: Algorithms and Implementation
Elementary Functions: Algorithms and Implementation
High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs
IEEE Transactions on Parallel and Distributed Systems
Efficient algorithms for solving overdefined systems of multivariate polynomial equations
EUROCRYPT'00 Proceedings of the 19th international conference on Theory and application of cryptographic techniques
Computational bit-width allocation for operations in vector calculus
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Bit-width allocation for hardware accelerators for scientific computing using SAT-modulo theory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust design methods for hardware accelerators for iterative algorithms in scientific computing
Proceedings of the 47th Design Automation Conference
Optimization of imprecise circuits represented by Taylor series and real-valued polynomials
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mixed Precision Processing in Reconfigurable Systems
FCCM '11 Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Numerical Data Representations for FPGA-Based Scientific Computing
IEEE Design & Test
A fused hybrid floating-point and fixed-point dot-product for FPGAs
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Accuracy-Guaranteed Bit-Width Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bounding Variable Values and Round-Off Effects Using Handelman Representations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Word-length optimization beyond straight line code
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Automating resource optimisation in reconfigurable design (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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The freedom over the choice of numerical precision is one of the key factors that can only be exploited throughout the datapath of an FPGA accelerator, providing the ability to trade the accuracy of the final computational result with the silicon area, power, operating frequency, and latency. However, in order to tune the precision used throughout hardware accelerators automatically, a tool is required to verify that the hardware will meet an error or range specification for a given precision. Existing tools to perform this task typically suffer either from a lack of tightness of bounds or require a large execution time when applied to large scale algorithms; in this work, we propose an approach that can both scale to larger examples and obtain tighter bounds, within a smaller execution time, than the existing methods. The approach we describe also provides a user with the ability to trade the quality of bounds with execution time of the procedure, making it suitable within a word-length optimization framework for both small and large-scale algorithms. We demonstrate the use of our approach on instances of iterative algorithms to solve a system of linear equations. We show that because our approach can track how the relative error decreases with increasing precision, unlike the existing methods, we can use it to create smaller hardware with guaranteed numerical properties. This results in a saving of 25% of the area in comparison to optimizing the precision using competing analytical techniques, whilst requiring a smaller execution time than the these methods, and saving almost 80% of area in comparison to adopting IEEE double precision arithmetic.