IEEE Transactions on Computers
Bidwidth analysis with application to silicon compilation
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
A novel approach to code analysis of digital signal processing systems
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Pebble: A Language for Parametrised and Reconfigurable Hardware Design
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
System Level Tools for DSP in FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Dynamic Precision Management for Loop Computations on Reconfigurable Architectures
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D Warping
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Quantitative analysis of floating point arithmetic on FPGA based custom computing machines
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
The Multiple Wordlength Paradigm
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Parameterised floating-point arithmetic on FPGAs
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGAs vs. CPUs: trends in peak floating-point performance
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
64-bit floating-point FPGA matrix multiplication
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Journal of VLSI Signal Processing Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Fast, Efficient Floating-Point Adders and Multipliers for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Word-length optimization beyond straight line code
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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This paper describes a method for customising the representation of floating-point numbers that exploits the flexibility of re-configurable hardware. The method determines the appropriate size of mantissa and exponent for each operation in a design, so that a cost functionn with a given error specification for the output relative to a reference representation can be satisfied. We adopt an iterative implementation of this method, which supports IEEE single-precision or double-precision floating-point representation as the reference representation. This implementation produces customised floating-point formats with arbitrary-sized mantissa and exponent. The tool follows a generic framework designed to cover a variety of arithmetic representations and their hardware implementations; both combinational and pipelined designs can be developed. Results show that, particularly for calculations involving large dynamic ranges, our tool can produce hardware that is smaller and faster when compared with a design adopting the reference representation.