Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Interval arithmetic and automatic error analysis in digital computing
Interval arithmetic and automatic error analysis in digital computing
Automated fixed-point data-type optimization tool for signal processing and communication systems
Proceedings of the 41st annual Design Automation Conference
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
IEEE Transactions on Computers
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Word-length optimization for differentiable nonlinear systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Symbolic noise analysis approach to computational hardware optimization
Proceedings of the 45th annual Design Automation Conference
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accuracy-Guaranteed Bit-Width Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel precision analysis approach, which optimizes the fractional wordlengths of signals in digital signal processing systems. Quantization-Operation-Error model is proposed to formulate the quantization error bound propagations through modules. Based on that, explicit relationship between output accuracy and hardware cost is built up, and a greedy search algorithm is proposed to find the minimum implementation cost while meeting output error constraint. Moreover, the greedy search steps can form a near pareto-optimal front, which can be used for a fast trade-off evaluation between output accuracy and implementation cost, such as area, power and latency. Experimental results and comparisons with existing state-of-the-art methods demonstrate the efficiency of proposed approach.