Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
MPFR: A multiple-precision binary floating-point library with correct rounding
ACM Transactions on Mathematical Software (TOMS)
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices
Journal of VLSI Signal Processing Systems
Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Automated Precision Analysis: A Polynomial Algebraic Approach
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Rapid computation of value and risk for derivatives portfolios
Concurrency and Computation: Practice & Experience
Combined word-length optimization and high-level synthesis of digital signal processing systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accuracy-Guaranteed Bit-Width Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multi-level Monte Carlo FPGA accelerator for option pricing in the Heston model
Proceedings of the Conference on Design, Automation and Test in Europe
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One of the main challenges when accelerating financial applications using reconfigurable hardware is the management of design complexity. This paper proposes a multi-level customisation framework for automatic generation of complex yet highly efficient curve based financial Monte Carlo simulators on reconfigurable hardware. By identifying multiple levels of functional specialisations and the optimal data format for the Monte Carlo simulation, we allow different levels of programmability in our framework to retain good performance and support multiple applications. Designs targeting a Virtex-6 SX475T FPGA generated by our framework are about 40 times faster than single-core software implementations on an i7-870 quad-core CPU at 2.93 GHz; they are over 10 times faster and 20 times more energy efficient than 4-core implementations on the same i7-870 quad-core CPU, and are over three times more energy efficient and 36% faster than a highly optimised implementation on an NVIDIA Tesla C2070 GPU at 1.15 GHz. In addition, our framework is platform independent and can be extended to support CPU and GPU applications.