Power macro-models for DSP blocks with application to high-level synthesis
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Efficient estimation of signal transition activity in MAC architectures
Proceedings of the 2002 international symposium on Low power electronics and design
Transition Activity Estimation for General Correlated Data Distributions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Power minimization is an important objective in present day VLSI design. Macromodels for power dissipation can be used to estimate power at a high-level of abstraction. High-level power estimation methods provide the designer with more flexibility to explore design trade-offs early in the design cycle. In this paper, we present closed-form analytical expressions for power consumption of macro-blocks in terms of the word-statistics. We present an analytical expression for total bit transition activity of a signal line in terms of the word-statistics. We also present analytical power models for macro-blocks in DSP architectures in terms of total bit transition activity and other parameters. Experimental results validating the analytical expressions are also included in this paper.