Universal approximation using radial-basis-function networks
Neural Computation
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Theoretical analysis of word-level switching activity in the presence of glitching and correlation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Low Power Digital CMOS Design
Efficient estimation of signal transition activity in MAC architectures
Proceedings of the 2002 international symposium on Low power electronics and design
Power Consumption in Point-to-Point Interconnect Architectures
Proceedings of the 15th symposium on Integrated circuits and systems design
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
High-level modeling of switching activity with application to low-power DSP system synthesis
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
Analytical estimation of signal transition activity from word-level statistics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Because of the increasing demand of low power digitalsystems, it is of great interest to extend the existing high-levelpower estimation techniques to handle flexible datamodels, as they appear in relevant applications. This paperpresents a data model and an algorithm suitable for estimatingthe transition activity in linear digital signal processingarchitectures. The technique extends previous proposedapproaches to handle a generalized class of correlatedand non-necessary Gaussian data distributions. Usingthe derived models, an estimation technique is proposedand evaluated for practical examples. Bit level simulationsresults show the adequate accuracy of the proposed approach.