Low power system scheduling and synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Domain-Specific Modeling for Rapid Energy Estimation of Reconfigurable Architectures
The Journal of Supercomputing
Energy-Efficient Computations on FPGAs
The Journal of Supercomputing
Tartan: evaluating spatial computation for whole program execution
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
A model-based extensible framework for efficient application design using FPGA
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Analytical High-Level Power Model for LUT-Based Components
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Switching activity models for power estimation in FPGA multipliers
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
A complete dynamic power estimation model for data-paths in FPGA DSP designs
Integration, the VLSI Journal
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Abstract: In this paper, we present a high-level power modeling technique to estimate the power consumption of re-configurable devices such as complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). For simplicity of reference, we simply refer to these devices as FPGAs. First, we capture the relationship between FPGA power dissipation and I/O signal statistics. We then use an adaptive regression method to model the FPGA power consumption. Such a high-level model can be used in the inner loop of a system-level synthesis tool to estimate the power consumed by different FPGA resources for different potential system-level synthesis solutions. It can also be used to verify the power budgets during embedded system design. With our high-level power model, the FPGA power consumption can be obtained very quickly. Experimental results indicate that the average relative error is only 3.1% compared to low-level FPGA power simulation methods.