A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Practical low power digital VLSI design
Practical low power digital VLSI design
The design of a low energy FPGA
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Power Modelling in Field Programmable Gate Arrays (FPGA)
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
A New Switch Block for Segmented FPGAs
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Trends in Low Power Digital System-on-Chip Designs
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Interconnect-Driven Short-Circuit Power Modeling
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
High-Level Power Modeling of CPLDs and FPGAs
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Switching activity analysis and pre-layout activity prediction for FPGAs
Proceedings of the 2003 international workshop on System-level interconnect prediction
Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Low-power technology mapping for FPGA architectures with dual supply voltages
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Interconnect capacitance estimation for FPGAs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HARP: hard-wired routing pattern FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Activity Packing in FPGAs for Leakage Power Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
Device and architecture co-optimization for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Vdd programmability to reduce FPGA interconnect power
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Exploiting temporal idleness to reduce leakage power in programmable architectures
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Methodology for high level estimation of FPGA power consumption
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Leakage control in FPGA routing fabric
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An analytical state dependent leakage power model for FPGAs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction
Proceedings of the 2006 international symposium on Low power electronics and design
Power-aware FPGA logic synthesis using binary decision diagrams
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Communication-oriented design space exploration for reconfigurable architectures
EURASIP Journal on Embedded Systems
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A power-aware algorithm for the design of reconfigurable hardware during high level placement
International Journal of Knowledge-based and Intelligent Engineering Systems - Adaptive Hardwarel / Evolvable Hardware
Word-length selection for power minimization via nonlinear optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA power reduction by guarded evaluation
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Exploiting clock skew scheduling for FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Technology mapping and clustering for FPGA architectures with dual supply voltages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes
Microelectronics Journal
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Circuits and architectures for field programmable gate array with configurable supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level power-performance tradeoffs for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Total power modeling in FPGAs under spatial correlation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate Area, Time and Power Models for FPGA-Based Implementations
Journal of Signal Processing Systems
Power estimation of dividers implemented in FPGAs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Net-length-based routability-driven power-aware clustering
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The VTR project: architecture and CAD for FPGAs from verilog to routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Power dissipation impact of the technology mapping synthesis on look-up table architectures
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A power-efficient processor core for reactive embedded applications
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Designing alternative FPGA implementations using spatial data from hardware resources
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper describes a flexible power model for FPGAs. The model estimates the dynamic, short circuit, and leakage power for a wide variety of FPGA architectures. Such a model will be essential in the design and research of next-generation FPGAs, where power will be one of the primary optimization goals. The model has been integrated into the VPR CAD flow, and is available to the research community for use in FPGA architectural and CAD tool experimentation.