Activity Packing in FPGAs for Leakage Power Reduction

Authors:
Hassan Hassan;Mohab Anis;Antoine El Daher;Mohamed Elmasry
Affiliations:
University of Waterloo, Canada;University of Waterloo, Canada;University of Waterloo, Canada;University of Waterloo, Canada
Venue:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2005

Citing 6
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Abstract

In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a connection-based packing technique by which the proximity of the logic blocks is accounted for, and the second algorithm is a logic-based packing approach by which the weighted Hamming distance between the blocks activities is considered. After both algorithms are analyzed, they are applied to a number of FGPA benchmarks for verification. Once the activity profiles are realized, sleep transistors are carefully positioned to contain the clustered blocks that share similar activity profiles. Finally, the percentage of the leakage power savings for each of the two algorithms is evaluated.