Precomputation-based Guarding for Dynamic and Leakage Power Reduction

Authors:
Afshin Abddollahi;Massoud Pedarm;Farzan Fallah;Indradeep Ghosh
Affiliations:
-;-;-;-
Venue:
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Year:
2003

Citing 0
Cited 5

Activity Packing in FPGAs for Leakage Power Reduction

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power optimization with power islands synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA power reduction by guarded evaluation

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Selective light Vth hopping (SLITH): bridging the gap between runtime dynamic and leakage power reduction

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a precomputation-based guarding technique toreduce both dynamic and static power consumptions in CMOS VLSIcircuits. More precisely, a high threshold sleep transistor isplaced in series with some portions of the circuit. Based on theinput values of the circuit, the sleep transistor is turned on andoff, thus, saving both dynamic and static power. We show how toapply this technique to a number of common arithmetic blocks,including comparators, adders and multipliers. Finally, dynamicguarding and sleep transistor activity reduction techniques forimproving the performance of the method are presented. Experimentalresults show 81% reduction in the power consumption of data pathmodules of a commercial VLIW processor can be achieved using ourtechniques. This is 20% higher than what has been achieved byprevious methods.