Power minimization of high-performance submicron CMOS circuits using a dual-Vdd dual-Vth (DVDV) approach

Cell selection from technology libraries for minimizing power

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems

IEEE Transactions on Computers

A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Activity Packing in FPGAs for Leakage Power Reduction

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Destructive-read in embedded DRAM, impact on power consumption

Journal of Embedded Computing - Issues in embedded single-chip multicore architectures

Exploiting GPU peak-power and performance tradeoffs through reduced effective pipeline latency

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture