Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Low-energy FPGAs: architecture and design
Low-energy FPGAs: architecture and design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
An FPGA architecture with enhanced datapath functionality
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
Device and architecture co-optimization for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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A novel approach for efficient implementation of applications onto reconfigurable architectures is introduced. The proposed methodology can applied both for designing an interconnection architecture as well as for making a thermal-aware placement. In the first case, the dominant parameters that affect performance and energy (segment length and switch boxes) are examined. This approach is based on finding the optimal wire length and then making exploration in order to determine the appropriate combination of multiple switch boxes. In the second case, a new technique for thermal-aware placement is introduced. The main goal of this technique is to spread out the power consumption across the whole device, as well as to minimize it. Both of the methodologies are fully-supported by the software tool called EX-VPR. For the purposes of this paper, the Energy× Delay Product (EDP) is chosen as selection criterion for the optimal interconnection network, while the total power consumption is the criterion for the thermal-aware routing. For the designing of the interconnection network we achieved EDP reduction by 45%, performance increase by 40% and reduction in total energy consumption by 8%, at the expense of increase of channel width by 20%. On the other hand, for the thermal-aware approach, we spread the heat and power across the whole FPGA, while we achieve about 20% reduction in total power consumption. In this case, the penalty in channel width is about 10%.