A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A high level SoC power estimation based on IP modeling
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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A study of the future trends in low-power System-on-Chip (SOC) designs is presented, based on the recently announced ITRS-2001 technology characteristics for both high-performance and low-power devices from 2001 to 2016. We forecast the logic/memory composition of a reference low-power PDA design with an area constraint of 1cm2 using both a bottom-up, power dissipation-constrained chip model and a top-down, design resource-constrained model. Together, these analyses indicate that without accelerated improvements in both chip design productivity and leakage power management, future SOC designs will be comprised of 80-90% memory, with the remaining logic blocks composed of special-purpose reusable IP cores, and a smaller fraction of the chip containing newly designed logic.