A high level SoC power estimation based on IP modeling

Authors:
David Elléouet;Nathalie Julien;Dominique Houzet
Affiliations:
Laboratoire I.E.T.R, UMR CNRS, Institut National des Sciences Appliquées, Rennes Cédex, France;Laboratoire L.E.S.T.E.R, FRE CNRS, Université de Bretagne Sud, Lorient Cédex, France;Laboratoire I.E.T.R, UMR CNRS, Institut National des Sciences Appliquées, Rennes Cédex, France
Venue:
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Year:
2006

Citing 4
Cited 0

Trends in Low Power Digital System-on-Chip Designs

ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Lossless and lossy minimal redundancy pyramidal decomposition for scalable image compression technique

ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 3 (ICME '03) - Volume 03
Power Consumption Modeling and Characterization of the TI C6201

IEEE Micro

Quantified Score

Hi-index	0.00

Visualization

Abstract

Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is estimated after RTL synthesis. We propose in this article a methodology based on measurements which allows to model the application power consumption with architectural and algorithmic parameters. So, the modeled applications can be added in a library in order to help the system designer to determine early in the design flow the best adequacy between high performances and low power consumption.