An empirical model for accurate estimation of routing delay in FPGAs
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FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
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WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The dynamic power consumed by a digital CMOS circuit is directly proportional to capacitance. In this paper, we consider pre-routing capacitance estimation for FPGAs and develop an empirical estimation model, suitable for use in power-aware placement, early power prediction, and other applications. We show that estimation accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also show that there is an inherent variability (noise) in the capacitance of nets routed using a commercial FPGA layout tool. This variability limits the accuracy attainable in capacitance estimation. Experimental results show that the proposed estimation model works well given the noise limitations.