The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Efficient circuit clustering for area and power reduction in FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A-priori wirelength and interconnect estimation based on circuit characteristics
Proceedings of the 2003 international workshop on System-level interconnect prediction
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
Interconnect capacitance estimation for FPGAs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Post Synthesis Level Power Modeling of FPGAs
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow
Proceedings of the 2006 international workshop on System-level interconnect prediction
Methodology for high level estimation of FPGA power consumption
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Interconnection lengths and delays estimation for communication links in FPGAs
Proceedings of the 2008 international workshop on System level interconnect prediction
Power estimation of embedded multiplier blocks in FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA power aware design flow
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A complete dynamic power estimation model for data-paths in FPGA DSP designs
Integration, the VLSI Journal
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A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to interconnections between modules and depends only on their mutual distance and shape. The power model has been characterized and verified with on-board power measurements, instead of using low-level estimation tools which often lack the required accuracy (observed errors go up to 350%). The results show that most of the errors of the presented power model lie within 20% of the physical measurements. This is an excellent result considering that in [2] it is shown that there is already a 20% variation in net capacitance due to the different routing solutions given by router for the same placement.