A wire length estimation technique utilizing neighborhood density equations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Characterization and parameterized random generation of digital circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Pre-layout estimation of individual wire lengths
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Congestion estimation during top-down placement
Proceedings of the 2001 international symposium on Physical design
On metrics for comparing routability estimation methods for FPGAs
Proceedings of the 39th annual Design Automation Conference
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow
Proceedings of the 2006 international workshop on System-level interconnect prediction
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Interconnection lengths and delays estimation for communication links in FPGAs
Proceedings of the 2008 international workshop on System level interconnect prediction
Predicting interconnect delay for physical synthesis in a FPGA CAD flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using circuit structural analysis techniques for networks in systems biology
Proceedings of the 11th international workshop on System level interconnect prediction
Floorplan-based FPGA interconnect power estimation in DSP circuits
Proceedings of the 11th international workshop on System level interconnect prediction
Cut-demand based routing resource allocation and consolidation for routability enhancement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Interconnect length estimation in VLSI designs: a retrospective
Proceedings of the 2014 on International symposium on physical design
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Interconnect prediction is very important for early feasibility studies in modern design flows. Most of the interconnect estimation techniques estimate average or total wirelength and some qualitative measure of routing demand for circuits. A-priori techniques estimate these characteristics without actually performing circuit placement. We propose a new a-priori interconnect and wirelength estimation methodology for island style FPGAs. For a given design, we estimate bounding box lengths of all nets for an optimized placement and the minimum number of tracks per channel required for successful routing on an FPGA device. We analyze the structural characteristics of circuits and limitations posed by the FPGA architecture to derive a consistent model for wirelength and routing demand estimation. Our results show that we have an average error of 11.6% w.r.to bounding box spans measured from the optimized layout using VPR [2]. Also, the number of routing tracks is predicted with an average error of 6.1% of the detailed routing results from VPR.