Pre-layout estimation of individual wire lengths
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Mixing buffers and pass transistors in FPGA routing architectures
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
A-priori wirelength and interconnect estimation based on circuit characteristics
Proceedings of the 2003 international workshop on System-level interconnect prediction
Incremental placement for layout driven optimizations on FPGAs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Incremental retiming for FPGA physical synthesis
Proceedings of the 42nd annual Design Automation Conference
A wire length estimation technique utilizing neighborhood density equations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Interconnection lengths and delays estimation for communication links in FPGAs
Proceedings of the 2008 international workshop on System level interconnect prediction
RAT: RC Amenability Test for Rapid Performance Prediction
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Floorplan-based FPGA interconnect power estimation in DSP circuits
Proceedings of the 11th international workshop on System level interconnect prediction
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper studies the difficulty of predicting interconnect delay in an industrial setting. Fifty industrial circuits, Altera's Quartus II CAD software, and Altera's Stratix and Stratix II FPGA architectures were used in the study. We show that there is a large amount of inherent randomness in a state-of-the-art FPGA placement algorithm. Thus, it is impossible to predict interconnect delay with a high degree of accuracy. Futhermore, we show that a simple timing model can be used to predict some aspects of interconnect timing with just as much accuracy as predictions obtained by running the placement tool itself. Finally, we examine the benefits of using the simple timing model in a timing driven physical synthesis flow, and attempt to establish an upper bound on these possible gains, given the difficulty of interconnect delay prediction.