Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
A-priori wirelength and interconnect estimation based on circuit characteristics
Proceedings of the 2003 international workshop on System-level interconnect prediction
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow
Proceedings of the 2006 international workshop on System-level interconnect prediction
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Introduction to Probability Models, Ninth Edition
Introduction to Probability Models, Ninth Edition
Floorplan-based FPGA interconnect power estimation in DSP circuits
Proceedings of the 11th international workshop on System level interconnect prediction
Wave-pipelined intra-chip signaling for on-FPGA communications
Integration, the VLSI Journal
A complete dynamic power estimation model for data-paths in FPGA DSP designs
Integration, the VLSI Journal
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Interconnect length estimation in VLSI designs: a retrospective
Proceedings of the 2014 on International symposium on physical design
| Hi-index | 0.00 |
This paper presents a new stochastic model to predictinterconnection lengths of communication links in FPGAs. Based on a stochastic inter-module routing model, expected length and variance of interconnections have been rigorously derived and, thus, delay can be computed based on the length estimate. The theoretical results are compared with experimental results of lengths and delays, which are obtained from implementations of links circuits in an FPGA. The stochastic model provides an accurate prediction of length with an average error of 6.3%. Results also show that theproposed model produces reliable predictions of delay and therefore the methodology can be applied to early stage planning and design optimization for communication links. Moreover, as a byproduct of this work, we also present in this paper an interesting phenomenon which we term "interconnection fringing". The fringing effect is attributed to the competition for routing resources in a communication link and will lengthen interconnections and, therefore, increase the delay.