A wire length estimation technique utilizing neighborhood density equations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Pre-layout estimation of individual wire lengths
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
A-priori wirelength and interconnect estimation based on circuit characteristics
Proceedings of the 2003 international workshop on System-level interconnect prediction
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
Toward the accurate prediction of placement wire length distributions in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Interconnection lengths and delays estimation for communication links in FPGAs
Proceedings of the 2008 international workshop on System level interconnect prediction
Interconnection analysis for standard cell layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Edge separability-based circuit clustering with application to multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and analysis of segmented routing channels for row-based FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A compilation of work related to a priori estimation of interconnect lengths in VLSI circuits is provided, with an emphasis on procedural wire length estimation methods that do not require knowledge of the circuit layout and instead rely on structural analysis of the circuit net list and stochastic modeling of the underlying placement and routing tools. Reviewed work includes references listed below.