Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Congestion aware layout driven logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
Fine granularity clustering for large scale placement problems
Proceedings of the 2003 international symposium on Physical design
Optimality, scalability and stability study of partitioning and placement algorithms
Proceedings of the 2003 international symposium on Physical design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Metrics for structural logic synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Generating synthetic benchmark circuits for evaluating CAD tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluation of placer suboptimality via zero-change netlist transformations
Proceedings of the 2005 international symposium on Physical design
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An effective clustering algorithm for mixed-size placement
Proceedings of the 2007 international symposium on Physical design
A novel net-degree distribution model and its application to floorplanning benchmark generation
Integration, the VLSI Journal
Towards scalable placement for FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Interconnect length estimation in VLSI designs: a retrospective
Proceedings of the 2014 on International symposium on physical design
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In this paper, we study the relationship between netlist structure and the efficiency of placers measured in terms of quality and stability of results. We analyze three types of placers: analytic, simulated-annealing-based and partition-based. We test the placers on industrial and synthetic benchmarks. Based on the observations and analyses of experimental results, we obtain several useful conclusions about relationships between netlist structure and placement efficiency of different types of placers.