RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Quantified suboptimality of VLSI layout heuristics
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
P-Complete Approximation Problems
Journal of the ACM (JACM)
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Global objectives for standard cell placement
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
On mismatches between incremental optimizers and instance perturbations in physical design tools
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Optimality, scalability and stability study of partitioning and placement algorithms
Proceedings of the 2003 international symposium on Physical design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Measurement of Inherent Noise in EDA Tools
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
Placement feedback: a concept and method for better min-cut placements
Proceedings of the 41st annual Design Automation Conference
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Multilevel global placement with congestion control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient and effective placement for very large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimality study of logic synthesis for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A tale of two nets: studies of wirelength progression in physical design
Proceedings of the 2006 international workshop on System-level interconnect prediction
Effective linear programming based placement methods
Proceedings of the 2006 international symposium on Physical design
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In this paper we introduce the concept of zero-change transformations to quantify the suboptimality of existing placers. Given a netlist and its placement from a placer, we formally define a class of netlist transformations that produce different netlists from the given netlist but have the same Half-Perimeter Wire Length (HPWL). Furthermore, the optimal HPWL value of the new netlists is no less than that of the original netlist. By applying our transformations and re-executing the placer, we can interpret any deviation in HPWL as a lower bound to the deviation from the optimal HPWL value. Such deviation is a measure of suboptimality. Using these transformations, the suboptimality of several existing academic and industrial placers is studied on the IBM benchmarks. Our results show that current placers are sub-optimal for zero-change transformations with deviations in HPWL by up to 32% on the IBM (version 1) benchmarks. The specific nature of our transformations also pinpoints possible directions for improvement in existing placers.